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aruppukottai, india
It's currently 1:33 PM here
Joined December 10, 2017
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Dhanabalan D.
@dhanabalang
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aruppukottai, india
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Researcher on Instrumentation, VLSI
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RM101.00 MYR
Electronics
Report Writing
Electrical Engineering
Circuit Design
Very-large-scale integration (VLSI)
A
•
Education
Ph.D.,
(6 years)
M.E.,
(2 years)
B.E.,
(4 years)
Qualifications
Certified LAbVIEW Associate Developer (CLAD)
National Instruments, USA
2013
National Instruments, USA conducts CLAD Examination to verify that the candidate has good stuff in LabVIEW.
Publications
FPGA Implementation of 8-bit Multiplier with Reduced Delay Time
International Journal of Computer and Communication Engineering
A design method for an 8-bit multiplication with reduced delay time is proposed. Normally, two numeric data can be multiplied by repeated addition. Carry generated because of addition affects the speed of multiplication since the present addition depends on the value of previous carry. To overcome this problem, addition with the help of multiplexer is introduced and the result is an increased speed in multiplication.
Design of parallel conversion multichannel analog to digital converter for scan time reduction of
Computer Standards & Interfaces (Elsevier)
The execution speed of a programmable logic controller (PLC) depends upon the number of analog and digital
input it scans, complication in ladder diagram and the time to store ladder diagram outputs in memory.
Next to the ladder diagram, scanning of analog signals consume enough time as they have to be converted into
digital. The hardware nature of field programmable gate array (FPGA) allows simultaneous conversion of all the analog signals.
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