Salvador C.

I am an experienced ASIC/FPGA design engineer. I have expertise on FPGA Design with Verilog/SystemVerilog, Python, OpenCL & Tcl. I have Tools experience of Xilinx VIVADO, ISE, VIVADO HLS, VIVADO SDK, SDSoC and Device experience of Xilinx Spartan, Zynq, Kintex and Vertex 7 Series and Ultrascale FPGA.