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baltimore, united states
It's currently 1:18 AM here
Joined August 14, 2013
1 Recommendation
Amirshahram H.
@freelancer867
5.1
5.1
100%
100%
baltimore, united states
100%
Jobs Completed
100%
On Budget
100%
On Time
23%
Repeat Hire Rate
MySQL Programmer - Software Architecture Developer - Java Developer
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Portfolio
Portfolio
Professional MPEG-2/MPEG-4 Encoder
Professional MPEG-2/MPEG-4 Encoder
Professional MPEG-2/MPEG-4 Encoder
Professional MPEG-2/MPEG-4 Encoder
Professional MPEG-2/MPEG-4 Encoder
FaceLock for Windows Phone
REAL-TIME FPGA BASED HUMAN IRIS RECOGNITION SYSTEM
Professional MPEG-2/MPEG-4 Encoder
Professional MPEG-2/MPEG-4 Encoder
Professional MPEG-2/MPEG-4 Encoder
Professional MPEG-2/MPEG-4 Encoder
Professional MPEG-2/MPEG-4 Encoder
FaceLock for Windows Phone
REAL-TIME FPGA BASED HUMAN IRIS RECOGNITION SYSTEM
Reviews
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Showing 1 - 5 out of 13 reviews
$120.00 USD
Matlab and Mathematica
Software Architecture
•
$25.00 USD
Matlab and Mathematica
H
•
$77.00 USD
C Programming
C++ Programming
•
$1,750.00 USD
C Programming
R
•
Experience
Senior system engineer
Jan 2009 - Jan 2011 (2 years)
Senior system engineer
Jan 2007 - Jan 2009 (2 years)
Education
Master of Software Engineering
(2 years)
Qualifications
Graduate Assistantship Scheme Award
Advanced Informatics School, Universiti Teknologi Malaysia
2012
Publications
Enhancement and Denoising Of Mammographic Images For Breast Disease Detection
EMPEC
In these two decades breast cancer is one of the leading cause of death among women. In breast cancer research, Mammographic Image is being assessed as a potential tool for detecting breast disease and investigating response to chemotherapy. In first stage of breast disease discovery, the density measurement of the breast in mammographic images provides very useful information. Because of the importance of the role of mammographic images the need for accurate and robust automated image enhancement technique
Field Programmable Gate Array System for Real-time IRIS Recognition
IEEE
Iris recognition is one of the most flawless recognition methods in biometrics. However, most of iris recognition algorithms are implemented based on sequential
operations running on central processing units (CPUs). In this article we propose a prototype design for iris recognition based on field-programmable gate array (FPGA) in order to improve iris recognition performance by parallel computing. Time consuming iris recognition sub-processes are fully implemented in parallel to achieve optimum performance
A Review on the Success Factors of E-Learning
SDIWC
E-learning as a network of sharing knowledge has changed dramatically the traditional concept of learning. To develop and implement a successful e-learning system, it is vital that institutions recognize the success factors of e-learning systems. This study reviewed the success factors and identified the most important technological aspects of e-learning. E-learning technological aspects were described and grouped into six categories, which are ease of access, interface design, level of interaction, system
Zero-Delay FPGA-Based Odd-Even Sorting Network
IEEE
Sorting is one of the most well-known problems in
computer science and is frequently used for benchmarking
computer systems. It can contribute significantly to the overall
execution time of a process in a computer system. Dedicated
sorting architectures can be used to accelerate applications
and/or to reduce energy consumption. In this paper, we propose
an efficient sorting network aiming at accelerating the sorting
operation in FPGA-based embedded systems. The proposed
sorting network is implemente
Real-Time FPGA-Based Human Iris Recognition Embedded System: Zero-Delay Human Iris Feature Extraction
Springer Berlin Heidelberg
Nowadays most of iris recognition algorithms are implemented based on sequential operations running on central processing units (CPUs). Conventional iris recognition systems use a frame grabber to capture a high quality image of an eye, and then system shall locate the pupil and iris boundaries, unwrap the iris image, and extract the iris image features. In this article we propose a prototype design based on pipeline architecture and combinational logic implemented on field-programmable gate array (FPGA). W
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